1. Field of the Invention
The present invention relates to a semiconductor substrate and a method to manufacture a semiconductor substrate, and more specifically to a method to manufacture an SOI (Silicon On Insulator) substrate which has a single-crystal silicon layer on an insulating layer and an SOI substrate manufactured by the method. The present invention relates in particular to an SOI substrate which is manufactured by a method referred to as SIMOX (Separation by Implanted Oxygen) method.
2. Related Background Art
Many researches have been made on formation of single-crystal silicon semiconductor layers on an insulating material since it is widely known as a silicon on insulator (SOI) technique and provides devices which have merits unavailable with ordinary bulk silicon substrates used to manufacture silicon integrated circuits. Speaking concretely, the SOI technique makes it possible to:
1. Facilitate to separate dielectric materials and highly integrate circuits. PA1 2. Obtain excellent resistance to radiation. PA1 3. Reduce floating capacities and accelerate speeds. PA1 4. Omit well process. PA1 5. Prevent latchup. PA1 6. Manufacture completely depletion-mode field effect transistors by thinning silicon layers. PA1 preparing a hydrogen-annealed single-crystal silicon substrate; PA1 forming an ion-implantation layer by implanting ions in the single-crystal silicon substrate; and PA1 forming a buried insulating film in the single-crystal silicon substrate.
(These merits are described detailedly, for example, in Special Issue: "Single-crystal silicon on non-single-crystal insulators", edited by G. W. Cullen, Journal of Crystal Growth, Volume 63, No. 3, pp. 429-590 (1983).)
Furthermore, it has been reported in these several years that SOI substrate permits enhancing a speed of MOSFET and lowering its power consumption (IEEE SOI conference 1994).
Furthermore, use of an SOI structure wherein an SOI layer is disposed on a support substrate by way of an insulating layer makes it possible to shorten a time for a device processing step since an element disposed on the insulating layer can be separated in a simpler process than an element formed on a bulk silicon wafer.
That is, the SOI substrate is expected not only to enhance performance of ICs but also to lower total manufacturing cost thereof including a wafer cost and a processing cost as compared with those of MOSFET ICs.
The researches on the SOI substrate has been made vigorously since about 1970s. Researches have been made vigorously on a method which hetero-epitaxially grows single-crystal Si on a sapphire substrate which is an insulating material (SOS: Sapphire On Silicon), a method which forms the SOI structure by isolating a dielectric material by oxidation of porous silicon (FIPOS: Fully Isolation by Porous Oxidized Silicon), a bonding method and an oxygen ion implantation method.
The oxygen ion implantation method is a method which was reported first by K. Izumi and is now referred to as SIMOX (K. Izumi, M. Doken and H. Ariyoshi: Electron Lett. 14, p. 593 (1978)). This method implants oxygen ions into a silicon wafer 103 on the order of 10.sup.17 to 10.sup.18 /cm.sup.2 as shown in FIG. 11A (FIG. 11B) and then forms an oxide layer 105 by annealing it at a high temperature on the order of 1320.degree. C. in an argon-oxygen atmosphere (FIG. 11C). As a result, the implanted oxygen ions couple with silicon around a depth corresponding to a projection range (R.sub.p) of the implanted ions, thereby forming a silicon oxide layer to obtain an SOI substrate 107. (An SOI substrate manufactured by utilizing the SIMOX will be referred to as an "SIMOX wafer" hereinafter.)
Many reports have been made on the SOI substrate that it enhances a speed of MOSFET and lowers its power consumption (described in detail in Proceedings of 1994 IEEE International Silicon-on-Insulator Conference).
Completely depletion-mode MOSFET manufactured by utilizing the SOI substrate is expected to have faster speed and consume power at a lower rate as a driving power is enhanced.
Furthermore, the SOI structure wherein an insulating layer is disposed under an element allows the element to be separated in a simpler process than an element formed on a bulk silicon wafer, thereby shortening a time for a device processing step.
That is, the SOI structure is expected not only to enhance performance of ICs but also lower total manufacturing cost thereof including wafer costs and processing costs as compared with those of MOSFET ICs disposed on bulk silicon wafers.
A CZ wafer is generally used as a silicon substrate to manufacture an SIMOX wafer. The CZ wafer is a single-crystal silicon substrate which is manufactured by a Czochrlski method.
The CZ wafer contains grown-in defects such as COPs (Crystal Originated Particles) and FPD (Flow Pattern Defect) which are peculiar to a bulk wafer.
The COPs (H. Yamamoto, Problems Posed on Large Diameter Silicon Wafers, 23rd Ultraclean Technology College (August 1996)) and FPD (T. Abe, Extended Abst. Electrochem. Soc. Spring Meeting Vol. 95-1, pp. 596 (May, 1995)) have sizes on the order of approximately 0.1 to 0.2 .mu.m.
The COPs and FPD will be described in detail later.
When a super LSI was manufactured with the CZ wafer, the defects such as the COPs conventionally influenced little on device characteristics since a device was manufactured with a sufficient margin for the grown-in defects.
Taking DRAMs as an example for which design rules have been changed to specify 0.5 .mu.m for 16M-DRAM and 0.35 .mu.m for 64M-DRAM, however, influences due to COPs are more and more remarkable on device characteristics and yields thereof.
Above all, it is said that a design rule will be modified to specify 0.1 to 0.15 .mu.m for 1G-DRAM.